The present invention relates to a raster operation apparatus for drawing display data on a display of an information processing apparatus at a high speed and, more particularly, to a raster operation apparatus for executing a drawing arithmetic operation at a high speed when windows or the like are synthesized and displayed.
Hitherto, in the window synthetic display or the like in a CRT display of the information processing apparatus, a raster operation apparatus is provided to produce new display data with regard to the overlapped portion of two display data. As shown on the left side of FIG. 1, it is now assumed that a source window 202 and a destination window 204 have been stored in a frame memory 200. As shown on the right side of FIG. 1, in the case where the source window 202 is moved to the position of the destination window 204 and is synthesized thereto, new data must be produced with respect to a region 206 in which both of those windows overlap. An arithmetic operation for this purpose is executed by the raster operation apparatus having a hardware construction of FIG. 2.
The frame memory 200 stores pixel data which is designated by addresses (X, Y). In case of the black and white display, since it is sufficient that each pixel data is constructed by one bit, one pixel data corresponds to one bit. On the other hand, in case of a color display, one pixel data is constructed by 24-bit data in which, for example, each of the R, G, and B data consists of eight bits. To simplify an explanation, it is now assumed that a black and white display is executed and one pixel corresponds to one bit as an example.
In FIG. 2, the raster operation apparatus comprises a source data storing section 210 having source registers 210-1 (SDR) and 210-2 (SDR), a shifter 212, a bit operating section 215, a destination register 216 (DDR), and selectors 208 and 214. The shifter 212 receives source data form the source registers 210-1 and 210-2 in parallel and circulatingly shifts the source data by only a designated bit amount, thereby generating shift outputs S1 and S2 on a source data unit basis. Specifically speaking, the shifter 212 is constructed by a gate switch network which can perform a switching control on a bit unit basis between the input bit train and the output bit train and functions as a kind of multiplexer. The bit operating section 215 overlaps the source data and the destination data by a bit arithmetic operation such as AND, OR, EOR, or the like, thereby producing new destination data. Each of the source registers 210-1 and 210-2 and the destination register 216 has a width of 16 bits. The shifter 212 has a width of 32 bits. Each of the shift outputs S1 and S2 has a width of 16 bits. Therefore, as a shift output S1 of the shifter 212, (0) to (15) bits of the shifter 212 having a width of 32 bits are generated. As a shift output S2, (16) to (31) bits are generated.
FIG. 3 shows the operation of the raster operation apparatus of FIG. 2. Attention is now turned to the head region of the source window 202. In this portion, source data (D1), (E1), (F1), and (G1) have been separately stored on the basis of a boundary unit as a physical memory unit of the frame memory 200. One boundary unit has a width of 16 bits. When the head region of the destination window 204 is seen, destination data (D2), (E2), (F2), and (G2) have similarly been stored on a boundary unit basis.
The raster operation to overlap the head source data (D1) to the destination data (D2) will now be considered. FIG. 4 shows a state in which the source data (D1) is moved as it is and is overlapped to the destination data (D2). Since the data process in this case is executed on a boundary unit basis, there is a possibility such that a bit deviation exists in the boundary of the width of 16 bits between the source data (D1) and the destination data (D2). In case of FIG. 4, there is a deviation of seven bits. In the raster operation, accordingly, it is necessary to produce the shift data (S1) shown in FIG. 5 by shifting the source data (D1) in FIG. 4 to the right by only seven bits, thereby matching the bit position to the destination data (D2). Such a bit shifting process is executed by the shifter 212 in FIG. 2.
FIG. 6 shows a function of the shifter 212 when the source data is shifted by seven bits as shown in FIG. 5. An input bit train 218 having a width of total 32 bits comprising the output data having a width of 16 bits from the source register 210-1 and the output data having a width of 16 bits from the source register 210-2 is shifted to the right by seven bits by the switching connecting operations of a group of internal gate switches and becomes an output bit train 220. Specifically, the (0) to (15) bits from the source register 210-1 in the input bit train 218 are shifted to the (7) to (22) bits in the output bit train 220. At the same time, nine bits among the (0) to (15) bits from the source register 210-2 in the input bit train 218 are shifted to the (23) to (31) bits in the output bit train 220 and remaining six bits are circulated to the left side of the output bit train 220 and become the (0) to (6) bits. If such a switching connecting state of the 7-bit shift has previously been realized in the shifter 212, by merely sequentially storing the source data into the source registers 210-1 and 210-2, the source data which was shifted by seven bits can be obtained by hardware.
FIGS. 7 to 10 show the shifting operation in the case where the source data (D1), (E1), (F1), and (G1) are sequentially read out from the source window 202 in the frame memory 200 of FIG. 3 and supplied to the shifter 212 which has already been set in the 7-bit shifting state in FIG. 6. In the raster operation apparatus in FIG. 2, when the selector 208 has already been switched to the source register 210-1 side and the source data (D1) is first read out from the frame memory 200 in the first cycle, the source data (D1) is stored into the source register 210-1 through the selector 208. In the second cycle, the destination data (D2) is read out from the frame memory 200 and stored into the destination register 216. In the third cycle, as shown in FIG. 7, the source data (D1) stored in the source register 210-1 passes through the shifter 212, so that it becomes the output bit train which has shifted to the right by seven bits. In this instance, the selector 214 selects the shift output (S1) and the bit operating section 215 fetches the shift data (S1) and destination data (D2) and executes a predetermined bit arithmetic operation and generates as new destination data (D3). The destination data (D3) from the bit operating section 215 is written to the position of the destination data (D2) in the frame memory 200 in the same third cycle.
The selector 208 is subsequently switched to the source register 210-2 side and the source data (E1) is read out from the frame memory 200 and stored. Subsequently, the destination data (E2) is stored into the destination register 216. In this case, the shifter 212 shifts the source data (E1) as shown in FIG. 8, the selector 214 selects the shift data (S2), and the bit operating section 215 executes a bit arithmetic operation with the destination data (E2) and forms new destination data (E3) and writes into the fame memory 200.
Subsequently, the selector 208 is switched to the source register 210-1 side and the source data (F1) is read out from the frame memory 200 and stored. Subsequently, the destination data (G2) is stored into the destination register 216. In this case, the shifter 212 shifts the source data (F1) as shown in FIG. 9. The selector 214 selects the shift data (S1). The bit operating section 215 executes a bit arithmetic operation with the destination data (F2) and forms new destination data (F3) and writes into the frame memory 200.
Further, the selector 208 is switched to the source register 210-2 side and the source data (G1) is read out from the frame memory 200 and stored. Subsequently, the destination data (G2) is stored into the destination register 216. In this case, the shifter 212 shifts the source data (G1) as shown in FIG. 10. The selector 214 selects the shift data (S2). The bit operating section 215 executes a bit arithmetic operation with the destination data (G2) and forms new destination data (G3) and writes into the frame memory 200.
In addition to a mode to synthesizing the source data and the destination data, the raster operation apparatus in FIG. 2 has a mode to merely move the position of the source data in the memory. Either one of those modes can be arbitrarily designated by using an OP code. In the mere moving mode of the source data, the cycle for reading out the destination data from the frame memory 200 and storing into the destination register 216 is omitted, by allowing the source data of the source register 210-1 or 210-2 to pass through the shifter 212, the source data is shifted by the bits corresponding to the bit deviation on the movement destination side, and the bit operating section 215 executes a bit arithmetic operation for generating as it is or inverting the shifted source data and generates as new destination data.
The timing chart of FIG. 11 shows the case where the source data (D1), (E1), (F1), and (G1) were merely moved in the frame memory 200 without any destination data. First, the source data (D1) is read in a T1 cycle. The output of the source register 210-1 is derived from a T2 cycle. In the T2 cycle, the shift data (S1) is supplied from the selector 214 to the bit operating section 215. The bit operating section 215 executes a bit arithmetic operation without any destination data and generates the new destination data (D3) and writes into the frame memory 200. In the next T3 cycle, the new destination data (D3) written in the frame memory 200 is read out and displayed on the CRT.
In the T3 cycle, the next source data (E1) is read out. In a T4 cycle, new destination data (E3) is derived as an output of the bit operating section 215 and written into the frame memory 200. In a manner similar to the above, processes are also executed as shown in T5 to T9 cycles with respect to the source data (F1) and (G1).
In the operations of such a conventional raster operation apparatus, however, after completion of the bit arithmetic operation, when the source data of the next boundary is read in, for example, each of the T2, T4, T6, and T8 cycles in which the new destination data is being written into the memory, the correct shift output from the shifter 212 is broken. Thus, the new destination data which is being written into the memory is broken. Therefore, until the memory writing operation in each of the T2, T4, T6, and T8 cycles is finished, no source data can be newly read. In each of the T2, T4, T6, and T8, an idling state 222 occurs in the memory access and the processing speed becomes slow due to the occurrence of such an idling state, so that the raster operation cannot be executed at a high speed.